1. Field of the Invention
The present invention relates to a driver circuit for amplifying current of an input signal of a first logical level or a second logical level and supplying the amplified signal to a load.
2. Description of the Prior Art
A driver circuit for amplifying current of a given signal and supplying the amplified current to a load has been used in various circuit devices. A driver circuit used in a Bi-CMOS (complementary metal oxide semiconductor) RAM (random access memory) disclosed in IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. SC-21, No. 5, Oct. 1986, pp. 681-684 is described by way of example.
Description is now made on a schematic structure of the Bi-CMOS.multidot.RAM.
The Bi-CMOS.multidot.RAM was developed to obtain a large capacity memory capable of performing high-speed operation and having a reduced consumed power, and comprises a combination of a bipolar and a CMOS. FIG. 1 illustrates a structure of a general RAM.
In FIG. 1, a plurality of word lines and a plurality of bit lines are arranged to intersect with each other in a memory cell array 50, memory cells being arranged at intersections of the word lines and the bit lines. A single word line in the memory cell array 50 is selected by an X address buffer decoder 52 and a single bit line in the memory cell array 50 is selected by a Y address buffer decoder 54, so that a memory cell provided at an intersection of the word line and the bit line is selected. Data is written into the selected memory cell or data stored in the memory cell is read out. Writing or reading of data is selected by a read/write control signal R/W applied to an R/W (read/write) control circuit 56. At the time of writing data, input data Din is inputted to the selected memory cell through the R/W control circuit 56. In addition, at the time of reading data, the data stored in the selected memory cell is detected and amplified by a sense amplifier 58, and provided to the exterior as output data Dout through a data output buffer 60.
In the Bi-CMOS.multidot.RAM, a memory cell array comprises an MOS transistor, and a peripheral circuit such as an address buffer decoder comprises a bipolar transistor or a combination of the bipolar transistor and the MOS transistor.
FIG. 2 is block diagram showing a structure of an address buffer decoder.
In FIG. 2, a plurality of address terminals 70 are connected to input terminals of a decoder circuit 78 through address buffer circuits 72, level converting circuits 74, and driver circuits 76, respectively.
Each of the address buffer circuits 72 comprises a bipolar ECL (emitter coupled logic) circuit, and an address signal at an ECL level (the potential at an "H" level=-0.9 V and the potential at an "L" level=-1.7 V) is inputted to each of the address terminals 70. Each of the level converting circuits 74 comprises a CMOS, and converts the address signal of the ECL level outputted from each of the address buffer circuits 72 into an address signal of an MOS level (the potential at an "H" level=0 V and the potential at an "L" level=-4.5 V). Each of the driver circuits 76 comprises a CMOS and a bipolar transistor having high driving ability. The decoder circuit 78 decodes a binary signal comprising a plurality of address signals and applies a selecting signal to one of a plurality of selecting lines 80. Therefore, a memory cell on the selecting line is selected.
FIG. 3 is a diagram showing a circuit structure of a driver circuit.
In FIG. 3, a CMOS inverter 93 comprising a PMOSFET (p-channel metal oxide semiconductor field effect transistor) 91 and an NMOSFET (n-channel metal oxide semiconductor field effect transistor) 92 has an input terminal connected to an input terminal 90. The CMOS inverter 93 has an output terminal connected to a base of a bipolar transistor 94. The bipolar transistor 94 has a collector coupled to a power supply potential V.sub.CC (0 V) and an emitter connected to an output terminal 98. On the other hand, an NMOSFET 95 has a gate connected to the input terminal 90, a drain connected to the output terminal 98 and a source connected to a drain of an NMOSFET 96 and a base of a bipolar transistor 97. The NMOSFET 96 has a gate connected to the output terminal 98 and a source coupled to a power supply potential V.sub.EE -4.5 V). The bipolar transistor 97 has a collector connected to the output terminal 98 and an emitter coupled to the power supply potential V.sub.EE.
Description is now made on operation of the driver circuit shown in FIG. 3.
If and when a signal applied to the input terminal 90 is changed from an "H" level to an "L" level, the PMOSFET 91 is turned on and the NMOSFETs 92 and 95 are turned off. Therefore, since the potential of the base of the bipolar transistor 94 attains the "H" level (V.sub.CC), the transistor 94 is turned on. At that time, since the NMOSFET 96 is turned on, the base potential of the bipolar transistor 97 attains the "L" level (V.sub.EE), so that the transistor 97 is turned off. Thus, an output signal derived from the output terminal 98 is changed from the "L" level to the "H" level.
On the other hand, if and when the signal applied to the input terminal 90 is changed from the "L" level to the "H" level, the NMOSFETs 92 and 95 are turned on and the PMOSFET 91 and the NMOSFET 96 are turned off. Therefore, the bipolar transistor 94 is turned off and the bipolar transistor 97 is turned on. Thus, the output signal derived from the output terminal 98 is changed from the "H" level to the "L" level.
Since large load capacitance is generally connected to the output terminal of the driver circuit, an output stage in the conventional driver circuit includes a bipolar transistor having high load-driving ability. Therefore, both of the "H" and "L" levels of the output signal derived to the output terminal 98 is decreased by voltage V.sub.BE between the base and the emitter of each of the bipolar transistors 94 and 97, as represented by a dotted line in FIG. 4.